1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory array layout structure and a memory structure.
2. Description of the Prior Art
Memory cell layouts are constantly miniaturized to be in accordance with product demands and the trends of high integration, high performance, and low power consumption. In a conventional dynamic random access memory (DRAM) layout, the word lines are perpendicular to the bit lines. Two word lines pass a same active area for forming two memory cells. A bit line contact plug is located between these two memory cells and electrically connected to a bit line. This bit line engages these two memory cells. Active areas in two adjacent rows are staggered from each other. Accordingly, an area for a repeating unit of 8 F2 can be obtained. F means feature size.
Although there are various conventional memory layouts, there is still a need for a novel memory layout structure and memory structure for high integration.